library ieee;
 use ieee.std_logic_1164.all;
 use ieee.std_logic_unsigned.all;

--- Assymetric delay line: --


-------------------------------------------------------------------------------
entity adelay_line is
-------------------------------------------------------------------------------
generic(
   num_of_buffers : integer := 1 -- minimal number is 1
);
port( 
      DI  : in   std_logic;   
      DO  : out  std_logic   
);           
-------------------------------------------------------------------------------
end adelay_line ;
-------------------------------------------------------------------------------

-------------------------------------------------------------------------------
architecture adelay_line_arch of adelay_line is
-------------------------------------------------------------------------------
	COMPONENT dl01d1  -- buffer 1x
	PORT(
	  i : IN  std_logic;
	  z : OUT std_logic
	);
	END COMPONENT;

	COMPONENT an02d1
	  PORT(
	  a1, a2 : IN std_logic;
	  z : OUT std_logic
	  );
	END COMPONENT;

signal del_line  : std_logic_vector(num_of_buffers downto 0);

begin

del_line(0) <= DI;

del_line_gen: for i in 0 to (num_of_buffers-1) generate

 u_del_line_dl01d1: dl01d1  -- buffer                         
  port map(
      i   => del_line(i),  
      z   => del_line(i+1)
 );

end generate;

u_an02d1: an02d1  -- 2-in and
port map(
      a1 => DI,
      a2 => del_line(num_of_buffers),
      z  => DO
);

-------------------------------------------------------------------------------
end adelay_line_arch;
-------------------------------------------------------------------------------                 

   
-------------------------------------------------------------------------------
configuration  adelay_line_cfg  of adelay_line is
-------------------------------------------------------------------------------
   for adelay_line_arch
   end for;
-------------------------------------------------------------------------------
end  adelay_line_cfg;              
-------------------------------------------------------------------------------
                 
